畢業(yè)設(shè)計(jì) 基于FPGA的無陀螺捷聯(lián)慣性導(dǎo)航系統(tǒng)設(shè)計(jì)

 摘要

無陀螺捷聯(lián)導(dǎo)慣性航導(dǎo)航系統(tǒng)（GFSINS）是指舍棄陀螺儀而直接把加速度計(jì)安裝在載體上，通過對加速度計(jì)輸出的比力信號(hào)進(jìn)行解算從而得到導(dǎo)航參數(shù)的慣性導(dǎo)航系統(tǒng)。捷聯(lián)慣導(dǎo)系統(tǒng)同平臺(tái)式慣導(dǎo)系統(tǒng)相比具有可靠性高、壽命長、節(jié)省體積空間等優(yōu)點(diǎn)。無陀螺捷聯(lián)慣導(dǎo)系統(tǒng)因?yàn)樯釛壛送勇輧x，與有陀螺的捷聯(lián)慣導(dǎo)系統(tǒng)相比具有低成本、低功耗、反應(yīng)速度快、動(dòng)態(tài)范圍大等優(yōu)點(diǎn)。隨著深亞微米技術(shù)的出現(xiàn)，現(xiàn)場可編程邏輯門陣列（FPGA）得到了迅猛發(fā)展，也使得可編程片上系統(tǒng)（SOPC）成為未來嵌入式系統(tǒng)設(shè)計(jì)技術(shù)發(fā)展的必然趨勢[1]。
本論文根據(jù)以九加速度計(jì)為配置方案的無陀螺捷聯(lián)導(dǎo)航計(jì)算機(jī)的特點(diǎn)和應(yīng)用要求，提出了基于FPGA的無陀螺捷聯(lián)慣性導(dǎo)航系統(tǒng)的硬件設(shè)計(jì)方案。系統(tǒng)主要包括數(shù)據(jù)采集模塊和數(shù)據(jù)解算模塊兩部分。數(shù)據(jù)采集模塊由STM32負(fù)責(zé)控制兩片AD7656將9個(gè)加速度計(jì)輸出的模擬信號(hào)轉(zhuǎn)換為數(shù)字信號(hào)。數(shù)據(jù)解算模塊采用Altera公司的FPGA芯片，利用SOPC技術(shù)完成FPGA內(nèi)部硬件邏輯的構(gòu)建，核心算法由高性能32位Nios II處理器完成，實(shí)現(xiàn)了浮點(diǎn)運(yùn)算。最后完成了原理圖和PCB設(shè)計(jì)，研制了實(shí)驗(yàn)樣機(jī)，為無陀螺捷聯(lián)慣性導(dǎo)航系統(tǒng)的進(jìn)一步研究工作奠定了基礎(chǔ)。

關(guān)鍵詞：GFSINS；導(dǎo)航計(jì)算機(jī)；FPGA；SOPC；STM32；雙口RAM
Abstract
Gyroscope Free Strapdown Inertial Navigation System(GFSINS) is a kind of Inertial Navigation System, accelerometers are derectly fixed in the carrier without using gyroscope. So acceleration is the exclusive in formation source, we can get all the navigation parameters by computing. Compared with The Platformtype Inertial Navigation System The Strapdown Inertial Navigation System is high reliability, longevity, small volume and so on. Compared with Strapdown Inertial Navigation System with gyroscope, GFSINS is low cost, low power, promote reaction, wide dynamic range and so on. With the emergence of submicron technology, FPGA chips have become more and more popular, thus making the system on a programmable chip (SOPC) design the mainstream technique in embedded system design field.
Take the features and application requirements of gyroscope free strapdown inertial navigation system with nine accelerometers into consideration, the thesis put forward a hardware design scheme of gyroscope free strapdown inertial navigation computer based on FPGA. The system includes data acquisition module and data decoding module two parts. In the data acquisition module, two AD7656 chips will change the analog signals from nine accelerometers into digital signals controlled by STM32. In the data decoding module, the internal hardware logic of FPGA is constructed by SOPC technology. The key algorithm is accomplished by high-performance 32-bit processor Nios II, in which realized the floating point arithmetic. Finally, the principle chart and PCB design is finished, making a test model, laying the foundation for the further research work of GFSINS.

Keywords：GFSINS；Navigation computer；FPGA；SOPC；STM32；DPRAM
目錄
摘要 I
Abstract II
第1章 緒論 1
1.1 慣性導(dǎo)航系統(tǒng)簡介 1
1.1.1 慣性導(dǎo)航系統(tǒng)的分類 1
1.1.2 無陀螺捷聯(lián)慣導(dǎo)系統(tǒng) 3
1.2 導(dǎo)航計(jì)算機(jī)發(fā)展簡介 3
1.3 論文的意義和主要內(nèi)容 4
第2章 系統(tǒng)總體設(shè)計(jì)方案 6
2.1 無陀螺捷聯(lián)慣導(dǎo)系統(tǒng)的工作原理 6
2.2 導(dǎo)航計(jì)算機(jī)的整體工作流程 7
2.2.1 導(dǎo)航計(jì)算機(jī)的性能要求 8
2.3 核心器件的選型 8
2.3.1 加速度計(jì)選型 8
2.3.2 A/D芯片選型 10
2.3.3 雙口RAM IDT 7133 13
2.3.4 微控制器選型 15
2.3.5 FPGA選型 16
2.4 本章小結(jié) 17
第3章 數(shù)據(jù)采集模塊 18
3.1 加速度計(jì)硬件連接設(shè)計(jì) 18
3.2 加速度計(jì)調(diào)理電路 19
3.2.1 減法電路 19
3.2.2 低通濾波電路 20
3.3 AD7656管腳連接設(shè)計(jì) 21
3.4 基于雙口RAM的雙CPU通訊電路 24
3.5 采集系統(tǒng)的供電電源設(shè)計(jì)方案 25
3.5.1 +5V到-5V電壓轉(zhuǎn)換電路 26
3.5.2 +5V到-3.3V電壓轉(zhuǎn)換電路 27
3.6 集成開發(fā)環(huán)境介紹 27
3.6.1 Real View MDK簡介 27
3.6.2  Vision IDE 28
3.7 本章小結(jié) 29
第4章 數(shù)據(jù)解算模塊 31
4.1 相關(guān)技術(shù)介紹 31
4.1.1 Nios II簡介 31
4.1.2 SOPC技術(shù) 32
4.1.3 Quartus II簡介 34
4.1.4 SOPC Builder簡介 36
4.2 FPGA內(nèi)部邏輯資源的設(shè)計(jì)過程 37
4.3 Nios II 集成開發(fā)環(huán)境（IDE） 43
4.4 本章小結(jié) 44
第5章 導(dǎo)航計(jì)算機(jī)系統(tǒng)調(diào)試 45
5.1 硬件調(diào)試 45
5.2 軟件調(diào)試 45
5.2.1 數(shù)據(jù)采集模軟件調(diào)試 45
5.2.2 數(shù)據(jù)解算模塊軟件調(diào)試 48
5.3 測試過程中出現(xiàn)的問題及解決的方法 49
5.4 本章小結(jié) 50