結(jié)構(gòu)化asic:方法與比較-外文翻譯.doc
約11頁(yè)DOC格式手機(jī)打開(kāi)展開(kāi)
結(jié)構(gòu)化asic:方法與比較-外文翻譯,結(jié)構(gòu)化asic:方法與比較-外文翻譯隨著制造工藝技術(shù)的不斷進(jìn)步,掩模的制造成本變得望而卻步的昂貴。結(jié)構(gòu)化asics能夠提供的價(jià)格和性能在asics和fpgas之間。他們?cè)谥械纫?guī)模的生產(chǎn)量上相當(dāng)有吸引力,并提供良好的知識(shí)產(chǎn)權(quán)保障。本文提出了一種結(jié)構(gòu)化asic方法,關(guān)于兩種金屬,一種掩模如何被制定,被描述。cad工具與as...
內(nèi)容介紹
此文檔由會(huì)員 叼著吸管的豬 發(fā)布
結(jié)構(gòu)化ASIC:方法與比較-外文翻譯
隨著制造工藝技術(shù)的不斷進(jìn)步,掩模的制造成本變得望而卻步的昂貴。結(jié)構(gòu)化ASICs能夠提供的價(jià)格和性能在ASICs和FPGAs之間。他們?cè)谥械纫?guī)模的生產(chǎn)量上相當(dāng)有吸引力,并提供良好的知識(shí)產(chǎn)權(quán)保障。本文提出了一種結(jié)構(gòu)化ASIC方法,關(guān)于兩種金屬,一種掩模如何被制定,被描述。CAD工具與ASICs的常規(guī)設(shè)計(jì)流程完全兼容,包括ASICs和FPGAs的延時(shí)性能比較也能給出。實(shí)施結(jié)構(gòu)化ASIC原型的LED背光LCD控制器是制造了0.13微米CMOS工藝。這是驗(yàn)證和功耗比ASIC設(shè)計(jì)。
Structured ASIC: Methodology and Comparison
Abstract—As fabrication process technology continues to Advance, mask set costs have become prohibitively expensive.Structured ASICs can offer price and performance between ASICs and FPGAs. They are attractive for mid-volume production and offer good intellectual property security.In this Paper a structured ASIC methodology, where 2 metal-and 1 via-mask are customised, is described.The CAD tools are fully compatible with conventional ASIC design flows and a comparison of area and delay performance with ASICs and FPGAs is given. A prototype structured ASIC implementing an LED-backlit LCD controller was fabricated in a 0.13μm CMOS process. It was verified and power consumption compared with an ASIC design.
隨著制造工藝技術(shù)的不斷進(jìn)步,掩模的制造成本變得望而卻步的昂貴。結(jié)構(gòu)化ASICs能夠提供的價(jià)格和性能在ASICs和FPGAs之間。他們?cè)谥械纫?guī)模的生產(chǎn)量上相當(dāng)有吸引力,并提供良好的知識(shí)產(chǎn)權(quán)保障。本文提出了一種結(jié)構(gòu)化ASIC方法,關(guān)于兩種金屬,一種掩模如何被制定,被描述。CAD工具與ASICs的常規(guī)設(shè)計(jì)流程完全兼容,包括ASICs和FPGAs的延時(shí)性能比較也能給出。實(shí)施結(jié)構(gòu)化ASIC原型的LED背光LCD控制器是制造了0.13微米CMOS工藝。這是驗(yàn)證和功耗比ASIC設(shè)計(jì)。
Structured ASIC: Methodology and Comparison
Abstract—As fabrication process technology continues to Advance, mask set costs have become prohibitively expensive.Structured ASICs can offer price and performance between ASICs and FPGAs. They are attractive for mid-volume production and offer good intellectual property security.In this Paper a structured ASIC methodology, where 2 metal-and 1 via-mask are customised, is described.The CAD tools are fully compatible with conventional ASIC design flows and a comparison of area and delay performance with ASICs and FPGAs is given. A prototype structured ASIC implementing an LED-backlit LCD controller was fabricated in a 0.13μm CMOS process. It was verified and power consumption compared with an ASIC design.