簡易邏輯分析儀的設(shè)計(jì).doc
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簡易邏輯分析儀的設(shè)計(jì),全文27頁約5300字論述翔實(shí)目錄一、 中文摘要 - - - - - - - - - - - - - - - - - - - - - - - - -3二、英文摘要 - - - - - - - - - - - - - - - - - - - - - - - - -4三、 概 述 - - - - - -...
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簡易邏輯分析儀的設(shè)計(jì)
全文27頁 約5300字 論述翔實(shí)
目錄
一、 中文摘要 - - - - - - - - - - - - - - - - - - - - - - - - -3
二、 英文摘要 - - - - - - - - - - - - - - - - - - - - - - - - -4
三、 概 述 - - - - - - - - - - - - - - - - - - - - - - - - 6
四、 總體方案設(shè)計(jì) - - - - - - - - - - - - - - - - - - - - - - - 6
4.1、 方案比較與選擇- - - - - - - - - - - - - - - - - - - - - -6
4.2、 統(tǒng)設(shè)計(jì)方案 - - - - - - - - - - - - - - - - - - - - - - - -7
五、 電路分析與設(shè)計(jì)- - - - - - - - - - - - - - - - - - - - - - -8
5.1 信號(hào)發(fā)生器- - - - - - - - - - - - - - - - - - - - - - - - -8
5.2 輸入電路- - - - - - - - - - - - - - - - - - - - - - - - - 10
5.3 采集與存儲(chǔ)電路-- - - - - - - - - - - - - - - - - - - - - 11
5.4 顯示控制電路- - - - - - - - - - - - - - - - - - - - - - - 11
5.5 利用示波器顯示：- - - - - - - - - - - - - - - - - - - - - -13
5.6 電源 - - - - - - - - - - - - - - - - - - - - - - - - - 15
六、 軟件設(shè)計(jì)- - - - - - - - - - - -- - - - - - - - - - - - -17
七、 系統(tǒng)測試分析 - - - - - - - - - - - - - - - - - - - - - - -19
八、 結(jié)論- - - - - - - - - - - - - - - - - - - - - - - - - -22
九、 結(jié)束語 - - - - - - - - - - - - - - - - - - - - - - - - -23
十、 參考文獻(xiàn)- - - - - - - - - - - - - - - - - - - - - - - - -24
十一、 致謝 - - - - - - - - - - - - - - - - - - - - - - - - - - 25
摘 要
邏輯分析儀是一種新型的數(shù)字測試儀器。它應(yīng)用于微機(jī)等數(shù)字系統(tǒng)的軟件、硬件調(diào)試，故障檢查，性能分析等過程中。它可以監(jiān)測硬件電路工作時(shí)的邏輯電平，并加以存儲(chǔ)，用圖形的方式直觀地表達(dá)出來，便于用戶檢測，分析電路設(shè)計(jì)中的錯(cuò)誤。在數(shù)字電路調(diào)試中，往往要測試多路信號(hào)波形，分析其邏輯關(guān)系。普通示波器最多只能測試兩路信號(hào)波形，而邏輯分析儀價(jià)格較高，我們設(shè)計(jì)的簡易邏輯分析儀造價(jià)低、性能高，具有一定的推廣價(jià)值。
本系統(tǒng)采用單片機(jī)和CPLD結(jié)合的方式。用CPLD制作信號(hào)發(fā)生和采集裝置，產(chǎn)生8路信號(hào)及數(shù)據(jù)采集。信號(hào)發(fā)生器的序列時(shí)鐘頻率可高于100HZ 。系統(tǒng)觸發(fā)方式具有單級(jí)觸發(fā)字和三級(jí)邏輯狀態(tài)分析觸發(fā)功能。其中觸發(fā)字可以通過鍵盤任意設(shè)定，觸發(fā)位置可調(diào)。
此邏輯分析儀能夠在示波器上清晰穩(wěn)定地顯示所采集到的8路信號(hào)波形和時(shí)間標(biāo)志線，并顯示觸發(fā)點(diǎn)的位置。單片機(jī)輸出可在上位機(jī)上顯示，能同時(shí)看到八路信號(hào)的波形和同一時(shí)刻不同信號(hào)的邏輯狀態(tài)。系統(tǒng)利用單片機(jī)來完成人機(jī)界面控制，信號(hào)觸發(fā)、分析、處理與變換。 8位輸入電路的輸入阻抗大于50kΩ,門限電壓16級(jí)
可調(diào)。每通道的存儲(chǔ)深度可達(dá)到32bit。單片機(jī)與CPLD的結(jié)合簡化了外圍硬件電路的設(shè)計(jì)，增加了系統(tǒng)的穩(wěn)定性和可靠性。
關(guān)鍵字：單片機(jī),CPLD,邏輯分析儀,示波器,信號(hào)發(fā)生器
ABSTRACT
Logic analyzer is a new-style digital testing instrument. It be used in the test of software and hardware of digital system, such as micro-computer,, fault-checked ,analysing-performance. It can surrey the voltage logic when system in full power. The instrument can save the result and describe it in figure for surveying and analyzing the error in circuit design. It need test multi-channel signal to analyse its logic relation in digital circuit testing .It only can test two signal for common oscillograph..Logic analyzer is expensive. Simple logic analyzer have low cost and high performance .It is worthy of using widely .
This system combines 89C51 and CPLD generating eight-channel signal and gathering data. The frequency of signal trigger’s clock is more than 100MHZ. The system trigger method has two ways one is single level trigger word the another is tri-level trigger function of logic analysis. Further more the trigger word can be modified through the keyboard. The trigger position can be changed freely.
This Logic analyzer output that is 8-channel signal wave gathered from outside and the time flag can be display on the oscillograph screen steadily. The oscillograph show the position of trigger point. The 89C51 communicates with PC to show it’s output. Users can observe eight channels signal wave and the signal states of different logic at the same time. The system accomplishs the interface of control between user and 89C51,signal touching off, analysis, disposing, and transform. The impedance of eight-channel signal input circuit is more than 50kΩ. The alterable voltage boundary is divided into16levels. The storage’s deep is up to 32bit. This combination of 89C51 and CPLD predigests the design of periphery instruments. This improvement let system became more stable and reliable.
Key words: micro-computer, CPLD, Logic analyzer,
oscillograph, signal generator.
部分參考文獻(xiàn)
《單片機(jī)應(yīng)用選編》
北京航空航天大學(xué)出版社
《新編電子電路大全》
中國計(jì)量出版社
《集成電路500例》
人民郵電出版社
全文27頁 約5300字 論述翔實(shí)
目錄
一、 中文摘要 - - - - - - - - - - - - - - - - - - - - - - - - -3
二、 英文摘要 - - - - - - - - - - - - - - - - - - - - - - - - -4
三、 概 述 - - - - - - - - - - - - - - - - - - - - - - - - 6
四、 總體方案設(shè)計(jì) - - - - - - - - - - - - - - - - - - - - - - - 6
4.1、 方案比較與選擇- - - - - - - - - - - - - - - - - - - - - -6
4.2、 統(tǒng)設(shè)計(jì)方案 - - - - - - - - - - - - - - - - - - - - - - - -7
五、 電路分析與設(shè)計(jì)- - - - - - - - - - - - - - - - - - - - - - -8
5.1 信號(hào)發(fā)生器- - - - - - - - - - - - - - - - - - - - - - - - -8
5.2 輸入電路- - - - - - - - - - - - - - - - - - - - - - - - - 10
5.3 采集與存儲(chǔ)電路-- - - - - - - - - - - - - - - - - - - - - 11
5.4 顯示控制電路- - - - - - - - - - - - - - - - - - - - - - - 11
5.5 利用示波器顯示：- - - - - - - - - - - - - - - - - - - - - -13
5.6 電源 - - - - - - - - - - - - - - - - - - - - - - - - - 15
六、 軟件設(shè)計(jì)- - - - - - - - - - - -- - - - - - - - - - - - -17
七、 系統(tǒng)測試分析 - - - - - - - - - - - - - - - - - - - - - - -19
八、 結(jié)論- - - - - - - - - - - - - - - - - - - - - - - - - -22
九、 結(jié)束語 - - - - - - - - - - - - - - - - - - - - - - - - -23
十、 參考文獻(xiàn)- - - - - - - - - - - - - - - - - - - - - - - - -24
十一、 致謝 - - - - - - - - - - - - - - - - - - - - - - - - - - 25
摘 要
邏輯分析儀是一種新型的數(shù)字測試儀器。它應(yīng)用于微機(jī)等數(shù)字系統(tǒng)的軟件、硬件調(diào)試，故障檢查，性能分析等過程中。它可以監(jiān)測硬件電路工作時(shí)的邏輯電平，并加以存儲(chǔ)，用圖形的方式直觀地表達(dá)出來，便于用戶檢測，分析電路設(shè)計(jì)中的錯(cuò)誤。在數(shù)字電路調(diào)試中，往往要測試多路信號(hào)波形，分析其邏輯關(guān)系。普通示波器最多只能測試兩路信號(hào)波形，而邏輯分析儀價(jià)格較高，我們設(shè)計(jì)的簡易邏輯分析儀造價(jià)低、性能高，具有一定的推廣價(jià)值。
本系統(tǒng)采用單片機(jī)和CPLD結(jié)合的方式。用CPLD制作信號(hào)發(fā)生和采集裝置，產(chǎn)生8路信號(hào)及數(shù)據(jù)采集。信號(hào)發(fā)生器的序列時(shí)鐘頻率可高于100HZ 。系統(tǒng)觸發(fā)方式具有單級(jí)觸發(fā)字和三級(jí)邏輯狀態(tài)分析觸發(fā)功能。其中觸發(fā)字可以通過鍵盤任意設(shè)定，觸發(fā)位置可調(diào)。
此邏輯分析儀能夠在示波器上清晰穩(wěn)定地顯示所采集到的8路信號(hào)波形和時(shí)間標(biāo)志線，并顯示觸發(fā)點(diǎn)的位置。單片機(jī)輸出可在上位機(jī)上顯示，能同時(shí)看到八路信號(hào)的波形和同一時(shí)刻不同信號(hào)的邏輯狀態(tài)。系統(tǒng)利用單片機(jī)來完成人機(jī)界面控制，信號(hào)觸發(fā)、分析、處理與變換。 8位輸入電路的輸入阻抗大于50kΩ,門限電壓16級(jí)
可調(diào)。每通道的存儲(chǔ)深度可達(dá)到32bit。單片機(jī)與CPLD的結(jié)合簡化了外圍硬件電路的設(shè)計(jì)，增加了系統(tǒng)的穩(wěn)定性和可靠性。
關(guān)鍵字：單片機(jī),CPLD,邏輯分析儀,示波器,信號(hào)發(fā)生器
ABSTRACT
Logic analyzer is a new-style digital testing instrument. It be used in the test of software and hardware of digital system, such as micro-computer,, fault-checked ,analysing-performance. It can surrey the voltage logic when system in full power. The instrument can save the result and describe it in figure for surveying and analyzing the error in circuit design. It need test multi-channel signal to analyse its logic relation in digital circuit testing .It only can test two signal for common oscillograph..Logic analyzer is expensive. Simple logic analyzer have low cost and high performance .It is worthy of using widely .
This system combines 89C51 and CPLD generating eight-channel signal and gathering data. The frequency of signal trigger’s clock is more than 100MHZ. The system trigger method has two ways one is single level trigger word the another is tri-level trigger function of logic analysis. Further more the trigger word can be modified through the keyboard. The trigger position can be changed freely.
This Logic analyzer output that is 8-channel signal wave gathered from outside and the time flag can be display on the oscillograph screen steadily. The oscillograph show the position of trigger point. The 89C51 communicates with PC to show it’s output. Users can observe eight channels signal wave and the signal states of different logic at the same time. The system accomplishs the interface of control between user and 89C51,signal touching off, analysis, disposing, and transform. The impedance of eight-channel signal input circuit is more than 50kΩ. The alterable voltage boundary is divided into16levels. The storage’s deep is up to 32bit. This combination of 89C51 and CPLD predigests the design of periphery instruments. This improvement let system became more stable and reliable.
Key words: micro-computer, CPLD, Logic analyzer,
oscillograph, signal generator.
部分參考文獻(xiàn)
《單片機(jī)應(yīng)用選編》
北京航空航天大學(xué)出版社
《新編電子電路大全》
中國計(jì)量出版社
《集成電路500例》
人民郵電出版社
