基于fpga和鎖相環(huán)4046實(shí)現(xiàn)波形發(fā)生器.doc
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基于fpga和鎖相環(huán)4046實(shí)現(xiàn)波形發(fā)生器,基于fpga和鎖相環(huán)4046實(shí)現(xiàn)波形發(fā)生器頁(yè)數(shù)：44字?jǐn)?shù)：17309摘要本設(shè)計(jì)采用fpga和鎖相環(huán)4046實(shí)現(xiàn)波形發(fā)生器。系統(tǒng)由波形產(chǎn)生模塊和可調(diào)頻率的時(shí)鐘產(chǎn)生模塊，數(shù)模轉(zhuǎn)換模塊和顯示模塊四部分組成。波形產(chǎn)生模塊完成三種波形的產(chǎn)生，并根據(jù)控制信號(hào)完成選定波形的輸出?？烧{(diào)頻率的時(shí)鐘產(chǎn)生模塊能夠產(chǎn)生具有不同頻率的方波clk...
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基于FPGA和鎖相環(huán)4046實(shí)現(xiàn)波形發(fā)生器
頁(yè)數(shù)：44 字?jǐn)?shù)：17309
摘 要
本設(shè)計(jì)采用FPGA和鎖相環(huán)4046實(shí)現(xiàn)波形發(fā)生器。系統(tǒng)由波形產(chǎn)生模塊和可調(diào)頻率的時(shí)鐘產(chǎn)生模塊，數(shù)模轉(zhuǎn)換模塊和顯示模塊四部分組成。波形產(chǎn)生模塊完成三種波形的產(chǎn)生，并根據(jù)控制信號(hào)完成選定波形的輸出?？烧{(diào)頻率的時(shí)鐘產(chǎn)生模塊能夠產(chǎn)生具有不同頻率的方波clk，用此方波作為時(shí)鐘完成輸出波形頻率的調(diào)整。顯示模塊用于顯示輸出波形的頻率。數(shù)模轉(zhuǎn)換模塊將波形產(chǎn)生模塊輸出的數(shù)字信號(hào)轉(zhuǎn)換為模擬信號(hào)；并完成濾波以及放大等功能。此設(shè)計(jì)的特點(diǎn)在于結(jié)合了直接數(shù)字頻率合成技術(shù)和鎖相技術(shù)各自的優(yōu)點(diǎn)，同時(shí)利用了FPGA的強(qiáng)大處理能力使系統(tǒng)易于實(shí)現(xiàn)，結(jié)構(gòu)簡(jiǎn)單。本設(shè)計(jì)能產(chǎn)生正弦波，三角波，占空比可調(diào)的方波以及它們的線性組合；頻率在100Hz~20KHz之間能以100Hz為步進(jìn)進(jìn)行調(diào)整；幅度可調(diào)范圍為0~5V。
關(guān)鍵詞：正弦波；三角波；占空比可調(diào)的方波；頻率可調(diào)；FPGA；鎖相環(huán)4046
Abstract
The system is designed to construct an Arbitrary Waveform Generator based on DDFS,with a PLL4046 and FPGA as the key,complimented by necessary analog circuit,so the system is very simple and convenience to realize.In the design ,there are four main module.The first module is oscillator,the modules are responsible for the formation of oscillogram and prefer waveform to output,in other words it can form square waveform,sinusoid waveform and delta waveform and output one kind waveform or the linear combination of several kind waveform;so this module is the key of the system.we use FPGA to realize this module,because FPGA have enough speed and logic unit to use ,and because of its programmable attribute,we can write procedure to complete our design,it is very convenience and reliable.The second module is the control of frequency.in this module,PLL(Phase Lock Loop)4046 plays a key role,iwhich realioze the change of frequency.In fact this module is also the key of the system,if there is not this module ,the frequency of the system can’t be changed and the frequency of waveform can’t be changed,too.PLL4046 have many function,for example:multiply frequency ,modulation.now we use it to multiply frequency,so the range of system frequency is very wide and having high definition.The third module is the digital-to-analog module.Obviously,it change the digital signal which is from the output port of FPGA into analogy signal by DAC0832,at the same time amplifer is used to amplify analogy signal and control of its amplitude range. The last module is demonstration module,its duty is to display the frequency of waveform.Then,by cascading every module,this system is realized. At last,this system can form square waveform,sinusoid waveform and delta waveform and linear combination of them.The frequency can be adjusted from 100Hz to 15KHz,its interval is 100Hz.It can gratify the request of the design.
Keywords:：sinusoid waveform；delta waveform ；square waveform；FPGA；PLL4046
目 錄
引言………………………………………………………………………………………1
1 設(shè)計(jì)任務(wù)……………………………………………………………………………1
1.1 基本要求………………………………………………………………………………1
1.2 發(fā)揮部分………………………………………………………………………………1
2 方案論證與比較……………………………………………………………………1
2.1 常見(jiàn)信號(hào)源制作方法原理……………………………………………………………1
2.2 常見(jiàn)信號(hào)產(chǎn)生電路……………………………………………………………………3
3 系統(tǒng)電路的設(shè)計(jì)……………………………………………………………………4
3.1 系統(tǒng)框圖及說(shuō)明………………………………………………………………………4
3.2 主要電路設(shè)計(jì)說(shuō)明……………………………………………………………………6
3.2.1晶體振蕩電路…………………………………………………………………………6
3.2.2倍頻電路………………………………………………………………………………6
3.2.3數(shù)模轉(zhuǎn)換和放大濾波電路……………………………………………………………7
3.2.4數(shù)碼管顯示電路………………………………………………………………………8
3.2.5 輸入去抖電路…………………………………………………………………………9
3.3 主要軟件設(shè)計(jì)說(shuō)明……………………………………………………………………10
3.3.1前端核心軟件設(shè)計(jì)……………………………………………………………………10
3.3.2波形產(chǎn)生模塊軟件設(shè)計(jì)………………………………………………………………12
3.4 主要元器件介紹………………………………………………………………………15
3.4.1FPGA介紹……………………………………………………………………………15
3.4.2鎖相環(huán)4046介紹……………………………………………………………………16
3.4.3VHDL介紹……………………………………………………………………………19
3.4.4MAX+PLUSII介紹…………………………………………………………………………20
4軟件仿真與硬件調(diào)試與測(cè)試 ……………………………………………………20
4.1 軟件部分仿真…………………………………………………………………………20
4.2 硬件調(diào)試………………………………………………………………………………22
4.3 硬件電路測(cè)試…………………………………………………………………………22
4.4 誤差分析………………………………………………………………………………23
5 工程設(shè)計(jì)………………………………………………………………………………23
6 制作……………………………………………………………………………………24
7 結(jié)論……………………………………………………………………………………25
謝辭………………………………………………………………………………………26
參考文獻(xiàn)…………………………………………………………………………………27
附錄………………………………………………………………………………………28
頁(yè)數(shù)：44 字?jǐn)?shù)：17309
摘 要
本設(shè)計(jì)采用FPGA和鎖相環(huán)4046實(shí)現(xiàn)波形發(fā)生器。系統(tǒng)由波形產(chǎn)生模塊和可調(diào)頻率的時(shí)鐘產(chǎn)生模塊，數(shù)模轉(zhuǎn)換模塊和顯示模塊四部分組成。波形產(chǎn)生模塊完成三種波形的產(chǎn)生，并根據(jù)控制信號(hào)完成選定波形的輸出?？烧{(diào)頻率的時(shí)鐘產(chǎn)生模塊能夠產(chǎn)生具有不同頻率的方波clk，用此方波作為時(shí)鐘完成輸出波形頻率的調(diào)整。顯示模塊用于顯示輸出波形的頻率。數(shù)模轉(zhuǎn)換模塊將波形產(chǎn)生模塊輸出的數(shù)字信號(hào)轉(zhuǎn)換為模擬信號(hào)；并完成濾波以及放大等功能。此設(shè)計(jì)的特點(diǎn)在于結(jié)合了直接數(shù)字頻率合成技術(shù)和鎖相技術(shù)各自的優(yōu)點(diǎn)，同時(shí)利用了FPGA的強(qiáng)大處理能力使系統(tǒng)易于實(shí)現(xiàn)，結(jié)構(gòu)簡(jiǎn)單。本設(shè)計(jì)能產(chǎn)生正弦波，三角波，占空比可調(diào)的方波以及它們的線性組合；頻率在100Hz~20KHz之間能以100Hz為步進(jìn)進(jìn)行調(diào)整；幅度可調(diào)范圍為0~5V。
關(guān)鍵詞：正弦波；三角波；占空比可調(diào)的方波；頻率可調(diào)；FPGA；鎖相環(huán)4046
Abstract
The system is designed to construct an Arbitrary Waveform Generator based on DDFS,with a PLL4046 and FPGA as the key,complimented by necessary analog circuit,so the system is very simple and convenience to realize.In the design ,there are four main module.The first module is oscillator,the modules are responsible for the formation of oscillogram and prefer waveform to output,in other words it can form square waveform,sinusoid waveform and delta waveform and output one kind waveform or the linear combination of several kind waveform;so this module is the key of the system.we use FPGA to realize this module,because FPGA have enough speed and logic unit to use ,and because of its programmable attribute,we can write procedure to complete our design,it is very convenience and reliable.The second module is the control of frequency.in this module,PLL(Phase Lock Loop)4046 plays a key role,iwhich realioze the change of frequency.In fact this module is also the key of the system,if there is not this module ,the frequency of the system can’t be changed and the frequency of waveform can’t be changed,too.PLL4046 have many function,for example:multiply frequency ,modulation.now we use it to multiply frequency,so the range of system frequency is very wide and having high definition.The third module is the digital-to-analog module.Obviously,it change the digital signal which is from the output port of FPGA into analogy signal by DAC0832,at the same time amplifer is used to amplify analogy signal and control of its amplitude range. The last module is demonstration module,its duty is to display the frequency of waveform.Then,by cascading every module,this system is realized. At last,this system can form square waveform,sinusoid waveform and delta waveform and linear combination of them.The frequency can be adjusted from 100Hz to 15KHz,its interval is 100Hz.It can gratify the request of the design.
Keywords:：sinusoid waveform；delta waveform ；square waveform；FPGA；PLL4046
目 錄
引言………………………………………………………………………………………1
1 設(shè)計(jì)任務(wù)……………………………………………………………………………1
1.1 基本要求………………………………………………………………………………1
1.2 發(fā)揮部分………………………………………………………………………………1
2 方案論證與比較……………………………………………………………………1
2.1 常見(jiàn)信號(hào)源制作方法原理……………………………………………………………1
2.2 常見(jiàn)信號(hào)產(chǎn)生電路……………………………………………………………………3
3 系統(tǒng)電路的設(shè)計(jì)……………………………………………………………………4
3.1 系統(tǒng)框圖及說(shuō)明………………………………………………………………………4
3.2 主要電路設(shè)計(jì)說(shuō)明……………………………………………………………………6
3.2.1晶體振蕩電路…………………………………………………………………………6
3.2.2倍頻電路………………………………………………………………………………6
3.2.3數(shù)模轉(zhuǎn)換和放大濾波電路……………………………………………………………7
3.2.4數(shù)碼管顯示電路………………………………………………………………………8
3.2.5 輸入去抖電路…………………………………………………………………………9
3.3 主要軟件設(shè)計(jì)說(shuō)明……………………………………………………………………10
3.3.1前端核心軟件設(shè)計(jì)……………………………………………………………………10
3.3.2波形產(chǎn)生模塊軟件設(shè)計(jì)………………………………………………………………12
3.4 主要元器件介紹………………………………………………………………………15
3.4.1FPGA介紹……………………………………………………………………………15
3.4.2鎖相環(huán)4046介紹……………………………………………………………………16
3.4.3VHDL介紹……………………………………………………………………………19
3.4.4MAX+PLUSII介紹…………………………………………………………………………20
4軟件仿真與硬件調(diào)試與測(cè)試 ……………………………………………………20
4.1 軟件部分仿真…………………………………………………………………………20
4.2 硬件調(diào)試………………………………………………………………………………22
4.3 硬件電路測(cè)試…………………………………………………………………………22
4.4 誤差分析………………………………………………………………………………23
5 工程設(shè)計(jì)………………………………………………………………………………23
6 制作……………………………………………………………………………………24
7 結(jié)論……………………………………………………………………………………25
謝辭………………………………………………………………………………………26
參考文獻(xiàn)…………………………………………………………………………………27
附錄………………………………………………………………………………………28
